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cyrf8935 wirelessusb?-nl 2.4 ghz low power radio cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-61351 rev. *j revised june 21, 2013 wirelessusb?-nl 2.4 ghz low power radio features fully integrated 2.4-ghz radio on a chip 1-mbps over-the-air data rate transmit power typical: 0 dbm receive sensitivity typical: ?87 dbm 1 a typical [1] current consumption in sleep state closed-loop frequency synthesis supports frequency-hopping spread spectrum on-chip packet framer with 64-byte first in first out (fifo) data buffer built-in auto-retry-acknowledg e protocol simplifies usage built-in cyclic redundancy check (crc), forward error correction (fec), data whitening supports dc ~ 12-mhz spi bus interface additional outputs for interrupt request (irq) generation digital readout of received signal strength indication (rssi) 4 4 mm quad flat no-leads (qfn) package, bare die, or wafer sales product description wirelessusb?-nl, optimized to operate in the 2.4-ghz ism band, is cypress's third generation of 2.4-ghz low-power rf technology, bringing the next level of low-power performance into a small 4-mm 4-mm footprint. wirelessusb-nl implements a gaussian frequency-shift keying (gfsk) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity. closed-loop modulation effectively eliminates the problem of frequency drift, enab ling wirelessusb-nl to transmit up to 255-byte payloads without repeatedly having to pay power penalties for re-locking the phase locked loop (pll) as in open-loop designs. among the advantages of wirelessusb-nl are its fast lock times and channel switching, along with the ability to transmit larger payloads. use of longer payload packets, compared to multiple short payload packets, can reduce overhead, improve overall power efficiency, and help alleviate spectrum crowding. combined with cypress's encore? family of usb and wireless microcontrollers, wirelessusb-nl also provides the lowest bill of materials (bom) cost solution for pc peripheral applications such as wireless keyboards and mice, as well as best-in-class wireless performance in other demanding applications such as toys, remote controls, fitness, automation, pres enter tools, and gaming. applications wireless keyboards and mice handheld remote controls wireless game controllers hobby craft control links home automation industrial wireless links and networks cordless audio and low-rate video note 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v in = 3 vdc, ta = +25 c.
cyrf8935 document number: 001-61351 rev. *j page 2 of 40 logic block diagram miso rst_n clk mosi spi_ss fifo pkt xtalo synthesizer brclk xtali v out v dd_io v in ant xtal osc x vco lna + bpf gfsk modulator ldo linear regulator pa image rej. mxr. spi registers framer antb gfsk demodulator gnd gnd pwr/ reset v dd1 ...v dd7 [2] note 2. brclk signal is available on bare die only, not packaged parts.
cyrf8935 document number: 001-61351 rev. *j page 3 of 40 contents pin configuration ............................................................. 4 pin descriptions ............................................................... 4 functional description ..................................................... 5 power-on and register initialization sequence ........... 5 enter sleep and wakeup ....... .............. .............. ......... 6 packet data structure ................................................. 6 fifo pointers .............................................................. 6 packet payload length ............................................... 6 framer: packet length handling ................................. 7 mcu or application handles packet length ............... 9 typical application ......................................................... 12 setting the radio frequency ..................................... 13 crystal oscillator ....................................................... 13 minimum pin count .. .............. .............. .............. ....... 14 reset pull-up ............................................................. 14 transmit power control ............................................. 14 reading rssi ............................................................ 14 automatic ack .................... ...................................... 15 receive crc and fec result .. .............. ........... ....... 15 sync word selection ................................................. 15 scramble on/off selection ..... ................................... 16 measuring receiver sensitivity ................................. 16 receive spurious responses ................................... 17 rf vco calibration ................................................... 17 regulatory compliance ................................................. 18 united states fcc .................................................... 18 register settings for test pu rposes .......................... 19 recommendations for pcb layout .............................. 19 antenna type and location .......................................... 19 ir reflow standard ......................................................... 20 register definitions ........................................................ 21 recommended register values ................................ 26 absolute maximum ratings .......................................... 28 operating range ............................................................. 28 electrical characteristics ............................................... 28 spi .................................................................................... 31 spi transaction formats and timing ........................ 31 specifications ............................................................ 32 electrical operating characteristics ............................. 33 state diagram ................................................................. 34 ordering information ...................................................... 35 ordering code definitions ..... .................................... 35 package diagram ............................................................ 36 acronyms ........................................................................ 37 document conventions ................................................. 37 units of measure ....................................................... 37 document history page ................................................. 38 sales, solutions, and legal information ...................... 40 worldwide sales and design s upport ......... .............. 40 products .................................................................... 40 psoc? solutions ...................................................... 40 cypress developer community ................................. 40 technical support ................. .................................... 40
cyrf8935 document number: 001-61351 rev. *j page 4 of 40 pin configuration figure 1. 24-pin qfn pinout (top view) pin descriptions antb ant pkt clk mosi miso rst_n xtali xtalo v out test3 fifo 18 17 16 15 1 2 3 4 5 6 test2 spi_ss 14 13 v in v dd_io 25 gnd 7 8 9 10 11 12 24 23 22 21 20 19 v dd3 v dd1 v dd2 v dd4 v dd5 gnd v dd6 v dd7 table 1. cyrf8935 24-pin qfn (4 4 mm) pinout pin number pin name type description 6, 7 test2, test3 -- reserved for factory test. do not connect. 1, 2, 5, 8, 9, 19, 22 v dd1 to v dd7 pwr core power supply voltage. connect all v dd pins to v out pin. 3, 4 antb, ant rf differential rf input/output. see typical application on page 12 for recom- mended antenna hookup. each of t hese pins must be dc grounded, 20 k ? or less 10 fifo o fifo status indicator bit 12, 25 gnd gnd ground connection 11 v dd_io pwr v dd for the digital interface 13 spi_ss i enable input for spi, active low. also used to bring device out of sleep state. 14 pkt o transmit/receive packet status indicator bit 15 clk i clock input for spi interface 16 mosi i data input for the spi bus 17 miso o/high-z data output (tristate when not active) 18 rst_n i rst_n low: chip shutdown to conserve power. register values lost rst_n high: turn on chip, registers restored to default value 20 v in pwr unregulated input voltage to the on-ch ip low drop out (ldo) voltage regulator 21 v out pwr +1.8 v output from on-chip ldo. connect to all v dd pins, do not connect to external loads. 23 xtalo ao output of the crystal oscillator gain block 24 xtali ai input to the crystal oscillator gain block
cyrf8935 document number: 001-61351 rev. *j page 5 of 40 functional description the cyrf8935 rf transceiver can add wireless capability to a wide variety of applications. the product is a low-cost, fully-integrated cmos rf transceiver, gfsk data modem, and packet framer, optimized for use in the 2.4-ghz ism band. it contains transmit, receive, rf synthesizer, and digital modem functions, with few external components. the transmitter supports digital power control. the receiver uses extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. the product transmits gfsk data at approximately 0-dbm output power. sigma-delta pll delivers high-quality dc-coupled transmit data path. the low-if receiver architectu re produces good selectivity and image rejection, with typical sens itivity of ?87 dbm or better on most channels. sensitivity on cha nnels that are integer multiples of the crystal reference oscillator frequency (12 mhz) may show approximately 5 db degradation. digital rssi values are available to monitor channel quality. on-chip transmit and receive fifo registers are available to buffer the data transfer with mcu. over-the-air data rate is always 1 mbps even when connected to a slow, low-cost mcu. built-in crc, fec, data whitening, and automatic retry/acknowledge are all available to simplify and optimize performance for individual applications. power-on and register initialization sequence for proper initialization at power up, v in must ramp up at the minimum overall ramp rate no slower than shown by t vin speci- fication in the following figure. during this time, the rst_n line must track the v in voltage ramp-up profile to within approxi- mately 0.2 v. since most mcu gp io pins automatically default to a high-z condition at power up, it only requires a pull-up resistor, as shown in figure 11 on page 14. when power is stable and the mcu por releases, and m cu begins to execute instruc- tions, rst_n must then be pulsed low as shown in figure 2 , followed by writing reg[27] = 0x 4200. during or after this spi transaction, the state machine status can be read to confirm framer_st= 1, indicating a proper initialization. figure 2. power-on and register programming sequence after rst_n transitions from 0 to 1, brclk [3] begins running at 12-mhz clock. after register initialization, cyrf893 5 is ready to transmit or receive. v in rst_n brclk spi_ss clock unstable clock stable spi activity t rsu t rpw t cmin (not drawn to scale) write reg[27]= 0x4200 t vin table 2. initialization timing requirements timing parameter min max unit notes t rsu ? 20 ms 2 < t vin ? ? 6.5 [ms/v] reset setup time necessary to ensure complete reset t rpw 1 10 s reset pulse width necessary to ensure complete reset t cmin 3 ? ms minimum recommended crystal oscillator and apll settling time t vin ? 6.5 ms/v maximum ramp time for v in , measured from 0 to 100% of final voltage. for example, if v in = 3.3 v, the max ramp time is 6.5 3.3 = 21.45 ms. if v in = 1.9 v, the max ramp time = 6.5 1.9 = 12.35 ms. note 3. brclk signal is available on bare die only, not packaged parts.
cyrf8935 document number: 001-61351 rev. *j page 6 of 40 figure 3. initialization flowchart enter sleep and wakeup when the mcu or application writ es to the cyrf8935 register 35[14] to ente r sleep mode and deasserts spi_ss, cyrf8935 enters the sleep state where current co nsumption is extremely low. later, when spi_ss is reasserted, cyrf8935 automatically wakes up from the sleep state. at this time the crystal oscillator is reactivated. the crystal oscillator takes 1 to 3 ms to become fu lly stable. during wakeup, there is no requirement to clear reg ister 35[14] and no requirement to hold spi_ss asserted. there are two sleep current choices available, selectable by reg[27] setting: 1 a [4] and 8 a. if you use the 1-a setting, vin must be greater than or equal to 3.0 vdc. if vin is ever expected to be < 3.0 vdc during sl eep, use the 8-a setting. the 1-a sleep setting should only be used for long-term sleep such as 8 to 10 seconds or more. to achieve the lowest sleep current, a special sleep stat e firmware patch is required. the patch is as follows: sleep patch: before writing register 35 to enter sleep, write reg[10]= 0x 8ffd, wait 30 s or more, then write reg[10] back to th e default value of 0x7ffd. next, write reg[35] to enter sleep, as usual. packet data structure figure 4. packet structure each over-the-air cyrf8935 packet is structured as follows: preamble: 1 to 8 bytes, programmable sync: 16/32/48/64 bits, programmable as device sync word trailer: 4 to 18 bits, programmable payload: tx/rx data crc:16-bit crc (optional) fifo pointers the fifo write pointer must be cleared before the application writes data to fifo for transmit. this is done by writing '1' to register 52[15]. after receiving a packet, the write pointer at register 52[13:8] indicates how many bytes of receive data are waiting in the fifo buffer to be read by the user mcu or the application. the fifo write pointer is automatically cleared when the receiver receives sync. the fifo read pointer is automatically cleared when the receiver receives sync, or after transmitting sync in transmit mode. packet payload length there are two ways to handle the tx/rx packet lengths in cyrf8935. if register 41[13] is equal to 1, the cyrf8935 internal framer detects the packet length based on the value of the first payload byte. if register 41 [13] is equal to 0, the first byte of the payload has no particular meaning, and packet length is determined by either tx fifo running empty or tx_en bit cleared (see ta b l e 3 ). initialize cyrf8935 at power-up mcu generates negative- going rst_n pulse wait crystal enable time initialize registers, beginning with reg[27] initialization done rst_n pulls up along with vin preamble sync word(s) trailer <== p a y l o a d ==> crc note 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v in = 3 vdc, ta = +25 c.
cyrf8935 document number: 001-61351 rev. *j page 7 of 40 the following sections show the detailed timing diagrams. all timing diagrams show active high for pkt and fifo flags. active l ow is also available through register 41[10] setting. framer: packet length handling the cyrf8935 framer handles packet length by setting register 41[13] = 1. the first byte of the payload is regarded as packet length (this length byte is not counted in the packet length). the cyrf8935 supports packet lengths up to 255 bytes. the framer handles tx/rx start and stop. transmit timing the tx timing diagram is shown in figure 5 . after mcu writes register 7[8]= tx_en = 1, the fr amer automatically generates the tx packet using payload data from the fifo register. the frequency (rf channel) will be as specified in register 7 at the time tx_en is written to 1. the mcu or application must load transmit data into the fifo register before the fram er sends trailer bits. you can do this by loading the transmit payload data into the fifo register either before or after writing tx_en = 1. for slower applications, it is easier to load the fifo register, and then write tx_en = 1. for the higher frame rate (faster) applications, write register 7 tx_en = 1, and then load the fifo register with payload data during the tx on delay time, as shown in figure 5 . if the packet length exceeds the fifo length, the mcu must write fifo data multiple times. the fifo flag indicates whether fifo is empty in transmit state. figure 5. tx timing diagram when register 41[13] = 1 (framer handles packet length) pkt and fifo flags are active high table 3. cyrf8935 configuration for packet length register 41[13] pack_length_en register 41[12] fw_term_tx cyrf8935 framer start/stop 0 (mcu or application handles packet length) 0 transmit stops only when register 7 tx_en = 0. see fw_term_tx = 0 (transmit) on page 10 for details. receive stops only when register 7 rx_en = 0. see fw_term_tx= 0 (receive) on page 11 for details. 1 transmit automatically stops whenever fifo runs empty. receive stops only when register 7 rx_en = 0. see receive timing on page 8. 1 (cyrf8935 framer handles packet length) x (do not care) the first byte of payload is regarded as packet length, 0 to 255 bytes. transmit automatically stops when all 0 to 255 bytes are transmitted. see framer: packet length handling on page 7 for details. spi_ss internal tx on 2 s tx on delay pa ramp up tx packet transmit data write reg. 7 fifo mcu fills fifo before fram er sends trailer bits. pkt = 1 after tx packet has been sent. fifo = 1 when fifo is empty pkt
cyrf8935 document number: 001-61351 rev. *j page 8 of 40 receive timing figure 6 shows the rx timing diagram. the receive process begins when the mcu writes regist er 7[7] = 1. at this time, the cyrf8935 framer turns on the receiver and waits while attempting to detect a valid syncword. the receive frequency is specified within register 7. the tw o register 7 fields of interest, rx_en and rf_pll_ch_no, may be sent to cyrf8935 during the same spi transaction. if sent in separate spi transactions, send the rf_pll_ch_no first, followed by rx_en. if a valid syncword is found, the cyrf8935 framer processes the packet automatically. when the received packet processing is complete, the cyrf8935 framer sets the state to idle. if the received packet length is longer than 63 bytes, the fifo flag goes active, which means the mcu must read out data from the fifo. a valid syncword might not always be found, either due to a weak signal, multi-path cancellation, or devices being out of range. to accommodate such a condition and to prevent lockup, the application or the mcu must inco rporate a 'receive timeout' timer to clear rx_en and retu rn to the idle state. figure 6. rx timing diagram when register 41[13] = 1 (framer handles packet length) pkt and fifo flags are active high spi_ss internal rx_on 2 s receive on delay rx packet received data write reg. 7 fifo pkt = 1 when rx packet has been received by framer. fifo = 1 when fifo is full. pkt
cyrf8935 document number: 001-61351 rev. *j page 9 of 40 mcu or application handles packet length when register 41[13] = 0, the first byte of the payload data has no special significance and the packet length depends on regis ter 41[12]. fw_term_tx = 1 if register 41[12] = 1, the cyrf8935 framer continues to compare the fifo write po int and the fifo read point during packet transmission. if the mcu or application stops writing data to fi fo, the framer eventually detect s that there is no data to send (fifo is empty), and cyrf8935 exits ?ceas e transmission? automatically (see figure 7 ). figure 7. tx timing when register 41[13:12] = '01b pkt and fifo flags are set as active high note when register 41[13] = 0 (mcu or application handles packet length ), never let fifo underflow or overflow. fifo full and empty thresholds can be controlled using register 40 fifo_emp ty_threshold and fifo_full_threshold settings. the best value depends on spi speed and the speed at which the mcu or application can stream the data into fifo. spi_ss internal tx on 2 s tx on delay pa on delay packet tx internal tx data write reg. 7 tx_ en = 1 mcu fills fifo before framer sends trailer bits . fifo = 1 when fifo is empty . framer will terminate tx when fifo write point equals fifo read point . pkt fifo
cyrf8935 document number: 001-61351 rev. *j page 10 of 40 fw_term_tx = 0 (transmit) when register 41[13:12] = '00b, the cyrf8935 framer does not st op packet transmission until mcu or application wr ites register 7[8] tx_en bit = 0. packet transmission cont inues even if fifo is empty (see figure 8 ). figure 8. tx timing diagram when register 41[13:12] = '00b pkt and fifo flags are shown active high note when register 41[13] = 0 (mcu or application handles packet leng th), never let fifo underflow or overflow. fifo full and empty thresholds can be controlled through register 40 fifo _empty_threshold and fifo_full_threshold settings. the best value depends on spi speed and the speed at which th e mcu or application can stream the data into fifo. spi_ss internal tx 2 s transmit delay pa on delay packet tx internal tx data write reg. 7 tx_ en = 1 pkt fifo mcu fills fifo before framer sends trailer bits . fifo = 1 when fifo is empty . framer terminates tx when mcu or application writes reg . 7 tx_ en = 0. write reg. 7 tx_ en = 0 2 s
cyrf8935 document number: 001-61351 rev. *j page 11 of 40 fw_term_tx= 0 (receive) when register 41[13] = 0, packe t reception starts when mcu or application writes register 7[7] rx_en = 1. at this time, the framer automatically turns on the receiver to the frequency and channel specified in register 7. after waiting for the internal synthesizer and receiver delays, the framer circuitry of the cyrf8935 begins searching the incoming signal for a syncword. when the syncword is detected, the framer sets the pkt flag active, and then starts to fill the fifo with receive data bytes. the pkt flag remains active until the mcu or application reads out the first byte of data from the fifo register. after the mcu or application reads the first byte of receive data, the pkt flag goes inactive until the next tx/rx period. with register 41[13:12] = '00b or '01b, the cyrf8935 framer always needs the mcu or applicatio n to write regist er 7[7] to 0 to stop the rx state. the rx timing diagram is shown in figure 9 . figure 9. rx timing diagram when register 41[13:12] = '00b or '01b pkt_flag and fifo_flag are active high spi_ss internal rx on 2 s internal rx on delay packet rx data internal rx data write reg. 7 pkt fifo pkt = 1 when syncword received. pkt = 0 when mcu/application reads fi rst byte from fifo register. write reg. 7 2 s fifo = 1 when fifo is full.
cyrf8935 document number: 001-61351 rev. *j page 12 of 40 typical application c7 15pf c6 4.7uf c5 0.10uf c8 15pf c1 0.10uf r3 2.2k c4 0.10uf spi_miso rst_n spi_mosi spi_ss fifo_flag pkt_flag +1.8v +3.3v +1.8v +1.8v y1 quartz xtal 12mhz c3 1.0pf l1 2.2nh +3.3v r2 680k 50 ohm 1 3 2 4 j1 sma r4 20k antenna conn. notes: 1. ant pin requires dc path to ground. if antenna or rf test equipment does not provide this, r4= 20k ohm is required. 2. max. input noise on vin: 50 mv pk. r1 51 note 1 xtalo 23 xtali 24 clk 15 gnd 12 pkt 14 vdd2 2 ant 4 antb 3 rst_n 18 miso 17 vdd3 5 vdd5 9 spi_ss 13 vdd4 8 mosi 16 vdd6 19 vdd_io 11 fifo 10 vin 20 vdd1 1 test2 6 test3 7 vout 21 vdd7 22 gnd 25 gnd 25 u1 cyrf8935 spi_clk r5 10k ceramic esr < 4 ohms note 2 +3.3v mcu interface
cyrf8935 document number: 001-61351 rev. *j page 13 of 40 setting the radio frequency programming by channel number is the easiest way to set frequency. in the cyrf8935, rf carrier frequency and rf channel number are always related by the expression: freq. = 2402 + ch. # channel number is loaded into bits [6:0] of register 7. bits 7 and 8 initiate the desired rx or tx operation, respectively. some sample register 7 examples are as shown in ta b l e 4 . during regulatory compliance testing, you can jump directly to another frequency any time without going through idle state. if you change between tx and rx, however, you must pass through idle state. for idle state, write register 7 to clear bits 8 and 7. tx or rx operation is initiated when register 7 bit 8 or 7 is set. radio frequency is also determined at that time. crystal oscillator the cyrf8935 contains the on-chip gain block for the quartz crystal frequency standard. quartz crystal application as shown in figure 10 on page 14, the series resistor rs limits power to the crystal and contributes to the phase-shift necessary for oscillation. the ideal rs value may need to be determined empirically, adjusted for certain crystal manufacturer part numbers and designs. the series equivalent combinations of c1 and c2 largely determine the capacitive load seen by the crystal, which should match the crystal vendor's specification. these capacitor values are chosen to center the crystal oscillator frequency at the correct value, 12 mhz. the feedback resistor rf from the buffer output to input serves to self-bias the on-chip buffer to the center of the linear region for maximum gain. verifying correct crystal oscilla tor frequency may require special test methods. because connecting a frequency counter probe to either xtali or xtalo adds capacitive loading and alters the crystal oscillation frequency, other methods must be used. for bare die applications involving cob packaging, use the brclk [5] test point to verify correct frequency of oscillation. this requires register 32[3:1] set accordingly (see register defini- tions on page 21). for 24-qfn packaged parts, the correct crystal frequency is determined by transmitting a continuous carrier frequency (see register settings for test purposes on page 19) and using a rf frequency counter to ensure correct frequency. irrespective of which method is used, initial tolerance should be within budget as recommended in ta b l e 5 , such that the total frequency error stays within budget. note for proper operation, the total frequency error must not exceed what is shown in ta b l e 5 . individual error contributions can be adjusted; for example 10+20+5+5=40, or 5+30+2+3=40. table 4. sample register 7 settings carrier frequency, mhz dut channel number (decimal) dut channel number (hex) tx setting: reg. 7 value for tx_en= 1 rx setting: reg. 7 value for rx_en= 1 2402 0 00 0100 0080 2403 1 01 0101 0081 2404 2 02 0102 0082 | | | | | 2434 32 20 0120 00a0 | | | | | 2441 39 27 0127 00a7 | | | | | 2480 78 4e 014e 00ce table 5. crystal specifications crystal parameter specification frequency 12.000 mhz initial frequency tolerance 15 ppm frequency tolerance over temperature 15 ppm frequency tolerance after aging 5 ppm frequency drift due to load cap. drift 5 ppm total 40 ppm equivalent series resistance 80 ? max resonance mode fundamental, parallel resonant load capacitance in accordance with external load capacitors (see c1 and c2 in figure 10 ) note 5. brclk signal is available on bare die only, not packaged parts.
cyrf8935 document number: 001-61351 rev. *j page 14 of 40 figure 10. simplified schematic of crystal oscillator note when crystal oscillator is constructed as shown in typical application on page 12, ta b l e 5 on page 13, and figure 10 , the oscillation frequency should be stable within 3 ms (max) after startup. minimum pin count when a low-cost mcu drives th e cyrf8935, the mcu pin count must be minimized. fifo pin: only needed when t he tx or rx packet length is greater than around 63 bytes, up to infinity. for short packets (< 63 bytes), fifo is not needed. pkt pin: gives a hardware indication of a packet received. if you are willing to poll register 48 for this information, then this pin is not needed. spi lines: all four lines are needed. reset pull-up for proper power-up initialization, the rst_n pin must have a pull-up to vin, as shown in figure 11 . the exact value of the 10-k pull-up resistor is not critical. the pull-up resistor ensures proper operation of the cyrf8935 internal-level shifter circuitry while power is applied. subsequently, the rst_npulse resets the internal registers to their default state. figure 11. reset pull-up circuit transmit power control ta b l e 6 lists recommended settings for register 9 for short-range applications, where reduced tran smit rf power is a desirable trade off for lower current.: reading rssi the cyrf8935 contains internal rssi circuitry that is roughly linearized to 1 db for every lsb. results are read from register 6[15:10], raw_rssi. see register definitions on page 21 for details. the framer must read the rssi register after the receiver is enabled and set on frequency using register 7, and after the rf pll has settled according to the correct receive frequency. clock logic xtal. osc. gain block cyrf8935 connect to frequency counter to verify correct crystal osc. frequency. (bare die only) xtalo xtali brclk c1 c2 crystal rs rf table 6. transmit power control power setting description typical transmit power (dbm) value of register 9 silicon id 0x1002 [6] silicon id 0x2002 [6] pa0 - highest power +1 0x1820 0x7820 pa2 - high power 0 0x1920 0x7920 pa4 - high power ?3 0x1a20 0x7a20 pa8 - low power ?7.5 0x1c20 0x7c20 pa12 - lower power ?11.2 0x1e20 0x7e20 rst_n xtalo 23 xtali 24 clk 15 gnd 12 pkt 14 vdd2 2 ant 4 antb 3 rst_n 18 miso 17 vdd3 5 vdd5 9 spi_ss 13 vdd4 8 mosi 16 vdd6 19 vdd_io 11 fifo 10 vin 20 vdd1 1 test2 6 test3 7 vout 21 vdd7 22 gnd 25 gnd 25 u1 cyrf8935 vin vin r5 10k note 6. silicon id can be read from register 31.
cyrf8935 document number: 001-61351 rev. *j page 15 of 40 the wait time between programming rx_en, and reading register 6, can be determined by any of the following methods, or any desired combination, depending on the application: wait in accordance with rf pll settling time spec. to be sure rf pll is settled. read register 3[12] rf_synth_lock to be sure cyrf8935 rf pll is settled. read register 48[7] syncword_recv to indicate the signal being received is a desired packet. note that rssi can be read without receiving a syncword. in other words, cyrf8935 rssi circuitry also responds to cw and interference signals. if the rssi feature is not needed, disable it to conserve receiver dc current budget. when register 11[9] is changed from 0 to 1, the receiver current consumption decreases by about 0.3 ma. figure 12. typical room temperature rssi response following is the pseudocode for measuring rssi: write reg11 = 0x0208 ;disable rssi before reading read rssi = reg6[15:10] ;do the read write reg11 = 0x0008 ;enable rssi for next measurement automatic ack the cyrf8935 provides an aut omatic retry/acknowledge feature. this means that if the tx packet does not successfully arrive at the receiving end, the tx end automatically attempts a given number of retries. in a weak signal environment, this feature makes the bit error rate (ber) appear to be zero at the expense of the frame erro r rate (fer). refer to state diagram on page 34 for details. to use automatic retry/acknowledge, see register definitions on page 21 for register 41[11] and register 35[11:8]. receive crc and fec result the cyrf8935 returns crc and fec error check status in register 48[15:14]. for conven ience, the entire top byte of register 48 is returned in the spi status word. these eight bits are normally available from the spi hardware block of the mcu or application, saving the time necessary to do an additional read of register 48 for the same information. crc is calculated only on the payload portion of the packet. crc_error only clears after another valid syncword is detected by the receiver or after transmission of a packet payload. sync word selection at the beginning of each packet, after transmission of a 01010101 preamble, is a sync word, programmable to be 16, 32, 48, or 64 bits long. for the devices to communicate, these must be programmed to the same value at both ends of the link. the sync word can be thought of as a mac address in this respect. in the cyrf8935 receiver, there is an adjustable tolerance for sync word bit errors that may occur. this adjustment is called syncword_threshold, set via register 40, bits 5:0. if set too tight, performance is good but less-than-optimum receive sensitivity and link budget is obt ained. if set too loose, frame errors increase because of false synchronization. the situation can sometimes be further complicated if the chosen sync word, combined with the 01010101 preamble, has unusually high auto correlation, or correlation with other devices that may be on the air on a different sync word network. this undesired condition is likely to happen when the sync word bits that immediately follow the 01010101 preamble continues the 1010... sequence. in such cases, it becomes difficult for the receiver to separate the actual sync word from the preamble. the solution is to either tighten the syncword_threshold, or choose a better sync word. some times increasing the sync word length is also an option. register 36 sets the sync word for the bits that immediately follow the preamble. if a false sync problem is observed, try changing this word first. the following table summarizes some recommended settings. table 7. recommended syncword_threshold settings application sync word length (see register 32) sync word selection recommended reg. 40 syncword_thr eshold setting (decimal) simple 32 better (almost every sync word must work) 1 32 good (most sync words work) 2 advanced 64 better (almost every sync word must work) 6 or tighter 64 good (most sync words work) 7
cyrf8935 document number: 001-61351 rev. *j page 16 of 40 scramble on/off selection the cyrf8935 incorporates a built-in hardware data scrambling and descrambling function. this function is designed to make the transmit data more random, removing long strings of continuous mark or space. when enabled, it causes payload data to be modified by a pn code that is initialized according to the setting of register 35 scramble_data. systems based on cyrf8935 will normally function either way, scramble on or off. setting scramble_on=1 will indeed cause a small 'token' increase in over-the-air security, similar to what wep adds to wifi. in other words, it renders the ota data coded, but it should not be considered highly secure. for truly secure applications, consider using scramble combined with other security algorithms. to function properly, both ends of the rf link need the same setting, enabled or disabled. both ends must also have the same register 35 scramble_data setting. measuring receiver sensitivity receive sensitivity and ber can be measured using these methods: method 1: link budget method in this method, another cyrf8935 or a compatible transceiver is used as a transmit packet source. it connects to the device under test (dut) through a calibrated attenuation path. the transmit power should also be known or measured. the receiver sensitivity can be calculated fr om the following equation, based on the largest rf attenuation that can be sustained between tx and rx, while maintaining adequate link performance. link_budget = (txp ? rxsens) [db] where txp = transmit power [dbm] rxsens = receive sensitivity [dbm] figure 13. measuring overall link budget, method 1 when using this method, make su re that the rf signal is not leaking around the attenuator or coupling directly into the receiver, which renders the atten uation setting meaningless. you can verify this by simply increasing the attenuation and verifying that the packets cease to be received at higher attenuator settings. rf leakage around the attenuator can be caused by: loose rf cable connector poorly shielded rf cables poor pcb layout at either tx or rx rf boards too close together coupling by or over the dc power leads note that interference from other 2.4-ghz services could be leaking into the test setup and degrade the ber measurement. when properly set up and working, the link budget method is a simple and reliable way to test and characterize cyrf8935 rf performance. test variations automatic loopback can be added to test both tx and rx in the same test. frequency hopping can be added to test over the design frequency range. method 2: packet signal generator method in this method, an rf signal generator is used as the packet source. the shielded, adjustable rf output of the signal generator connects to the receiver input. the signal generator must have digital pattern storage ability for the modulation. a packet of valid data is downloaded into the signal generator, and these packets are repetitively s ent to the cyrf8935 receiver under test. an mcu or pc pr ogram monitors the cyrf8935 pkt flag signal, which causes t he mcu or pc to download each packet as it is received, co mpare the packet against the expected values, and report the packet statistics to the end user. mcu cyrf 8935 cyrf 8935 dut packet tx mcu variable atten. trilithic bma-35110 or equiv. packet rx
cyrf8935 document number: 001-61351 rev. *j page 17 of 40 figure 14. measuring receiver sensitivity with signal generator, method 2 in this setup, the signal generator is set as follows: modulation: gfsk, 2-level, bt = 0.5, peak deviation 320 khz, symbol rate 1 msps. frequency, amplitude: as required for test. receive spurious responses this receiver, like many other low-cost receivers, may exhibit spurious responses in-band, often at multiples of certain digital frequencies. in the case of the cyrf8935, this response sometimes occurs at multiples of 4 mhz or four channels, offset from the desired receiver passband. during frequency hopping, a signal may be found on the wrong frequency, causing incorrect hopping synchronization. the workaround for this is to program one of the payload bytes to contain the channel number on which the packet is being transmitted. when a packet is received, this byte is checked to determine if it matches the rece ive channel setting. if not, the packet should be discarded. rf vco calibration over-the-air transmit and receive frequencies for the cyrf6935 rf transceiver are derived from the 12 mhz crystal oscillator, multiplied up by the in ternal fractional-n rf pll. low phase noise is obtained by keeping the pll k vco relatively low. in order for the vco to cover the desired frequency range over the expected v dd , temperature, and process extremes, the vco must be calibrated prior to use. the cyrf8935 contains a fully automatic calibration algorithm, but the algorithm does require approximately 150 us extra time, compared to automatic calibration turned off. rf signal generator with pattern gen. cyrf 8935 dut packet transmitter packet data pattern downloaded into signal generator packet receiver pc programmer rs-232 term. mcu bd.
cyrf8935 document number: 001-61351 rev. *j page 18 of 40 regulatory compliance united states fcc when operating in the 2402- to 2480-mhz band, the second and third harmonics always fall into what is defined in 47cfr, section 15.205 as ?restricted bands of operation?. the field strength of radiated emissions gr eater than 1 ghz in a restricted band mus t not exceed 500 v/m at a distance of 3 meters. using the equation fo r free space propagation, you can translate the field strength to an equivalent rf power level at the dut, if an assumption is made regarding the effective antenna gain at the second and third har monic frequencies. figure 15. calculation of maximum spurious level the antenna gain assumption of +6 dbi is based on the fact that the measurement requires that the positi on of the dut and measurement antennae be maximized to yield the highest spurious signal. since the second and third harmonics, by definition, fa ll on integer multiples of the carrier wave length, many common dut antennae may have good, usable gain at higher frequencies such as 0 dbi. accounting for the maximization of the measurement, +6 dbi is a good, conservative antenna gain for harmonic frequenc ies. in practice, harmonic emissions are much less of a problem, pr imarily because the antenna is not specifically optimized for suc h harmonics. the calculation in figure 15 shows the maximum spurious level at the antenna as ?47 dbm. because the typical second harmonic is specified as ?45 dbm, it follows that an additional 2 db attenuat ion could be required. however, no additional attenuation is re quired to pass the fcc-radiated emissions test . individual test results may vary. ta b l e 8 lists a summary of fcc precompliance test results. the an tenna used is a common half-wave end-fed dipole. the results easily pass the u.s. fcc test for a part 15.247 device. if there is a problem with q ualification because of spurious emissions in restricted bands, you can add a filter, or per haps reduce tx power through register 9. table 8. fcc test results run no. mode channel power setting measured power test performed limit result/margin 1a non hopping 2402 mhz default na restricted band edge (2390 mhz) fcc part 15.209 / 15.247(c) 46.8 db ? v/m at 2390.0 mhz (?7.2 db) default na radiated emissions (1?0 ghz) fcc part 15.209 / 15.247(c) 45.7 db ? v/m at 4804.1 mhz (?8.3 db) 1b non hopping 2441 mhz default na radiated emissions (1?18 ghz) fcc part 15.209 / 15.247(c) 45.0 db ? v/m at 4882.2 mhz (?9.0 db) 1c non hopping 2480 mhz default na restricted band edge (2483.5 mhz) fcc part 15.209 / 15.247(c) 47.8 db ? v/m at 2484.1 mhz (?6.2 db) default na radiated emissions (1?10 ghz) fcc part 15.209 / 15.247(c) 45.3 db ? mv/m at 4960.1 mhz (?8.7 db) paramete r unit of m easure field strength 54.0 dbv/m o r 501 v/m o r 0.501 mv/m tx antenna gain over isotropic 6 dbi o r 3.981071706 powe r ratio imp edance of free space 377 ohm s o r 120*pi ohm s dista nce 0.003 km o r 3m result t x pwr, desired sign al 0 dbm o r 0.001 w tx pwr, undesired sp urious -47.2 dbm o r 1.89287e- 08 w or -47.2 dbc
cyrf8935 document number: 001-61351 rev. *j page 19 of 40 register settings for test purposes to pass various regulatory agency emc tests, the dut may need to enter various test states as shown below. after loading the recommended register values shown in table 12 on page 26, load the registers in the order shown in the following table. recommendations for pcb layout though the pcb layout is not too critical, here are some recommendations: rf path: adhere closely to the recommended reference design circuit. clock traces: keep the quartz crystal traces simple and direct. the self-bias resistor should be close to the xtali and xtalo pins. the oscillation loop, consisting of the series resistor and crystal, should be a simple, small loop. the crystal-loading capacitors should be near the crystal. the ground connection to these capacitors must be good, clean, and quiet. this prevents noise from being injected into the oscillator. it is best to have one ground plane for the entire rf section. power distribution and decoupling: capacitors should be located near the v dd pins, as shown in typical application on page 12. antenna placement: when using an antenna, follow the manufacturer's recommendation regarding layout. digital interface: to provide a good ground return for the digital lines, it is a good idea to provide at least two pins for ground on the digital interface connector. good grounding between rf and mcu can help reduce noise 's een' at the antenna, thus improving performance. antenna type and location the most significant factor affecting rf performance for the cyrf8935 or any other over-the-air rf device is the antenna type, placement, and orientation. antenna gain is normally measured with respect to isotropic, that is, an ideal radiator that sends or receives power equally to or from any direction. an ideal antenna choice for most low-power, short-range wireless applications is the theoretic al isotropic reference antenna. unfortunately, these do not exist in practice. a simple dipole with a theoretical gain of +2 dbi is usually a good choice. however, you should take care when placing the antenna, because dipole antennas have a radiation pattern where the null can be very deep. the antenna must be kept away from human tissue, particularly sensitive spots like the heart, brain, and eyes. violating this design principle makes the end product perform poorly and can be dangerous for the user. refer to www.fcc.gov/oet/rfsafety for guidance on this subject . for best operation, design the product so that the main antenna radiati on is away from the body, or at least not proximity-loaded by the human body or dielectric objects within the product. remember to keep the antenna away from clock lines and digital bus signals; otherwise, harmonics of the clock frequency will jam certain receive frequencies. table 9. register settings for test purposes test state notes register settings tx continuously, cw mode primarily used to verify proper crystal oscillator frequency. the tx turns on and stays on continuously. there will be no on/off bursting of the carrier. modulation will be absent. carrier frequency will be half-way between mark and space. occasionally used during emc testing. reg. 11= 0x8008 (cw_mode= 1) reg. 41= 0xc000 (scramble_on= 1, pack_length_en= 0, and fw_term_tx= 0) reg. 7 as shown in ta b l e 4 on page 13. tx continuously, random data mode during emc testing, this is the most commonly used tx test. modulation will be normal, gfsk. tx data will continu- ously cycle through the fifo data bits. a data scram- bling function will be applied. in other words, even if the fifo has all zeros (not yet loaded with data), tx data will appear random. radiated emissions resemble normal operation except that the carrier is on continu- ously, which significantly speeds up testing. reg. 11= 0x0008 (cw_mode= 0) reg. 41= 0xc000 (scramble_on= 1, pack_length_en= 0, and fw_term_tx= 0) reg. 7 as shown in ta b l e 4 on page 13. rx continuously sometimes required for emc testing. reg. 41= 0xc000 (pack_length_en= 0, and fw_term_tx= 0) reg. 7 as shown in ta b l e 4 on page 13. tx and rx off (idle state) when neither tx nor rx is desired. reg. 7: clear bits 8 and 7. reg. 7 binary: xxxx xxx0 0xxx xxxx (x = don?t care)
cyrf8935 document number: 001-61351 rev. *j page 20 of 40 ir reflow standard reference: ipc/jedec j-std-020d.1 figure 16. recommended ir reflow profile liquidous temp. tl= 217 tp = 250 +0, -5 30 seconds (see jedec j-std-020 latest rev.) ramp-up 3 c per second (max) ramp-down 6 c per sec. (max) tsmax = 200 temp: c tsmin = 150 60 to 150 seconds 60 to 120 seconds t= 25 8 minutes max. time
cyrf8935 document number: 001-61351 rev. *j page 21 of 40 register definitions the following registers are accessed using the spi protocol. some of the internal registers and bit fiel ds are not intended for end-user adjustment . such registers are not described here a nd should not be altered from the factory-recommended value table 10. rf register information bit no. bit name description register 3 ? read only 15:13 (reserved) (reserved) 12 rf_synth_lock indicates the phase lock status of rf synthesizer. 1: locked 0: unlocked 11:0 (reserved) (reserved) register 6 ? read only 15:10 raw_rssi[5:0] indicates 6-bit raw rssi value from analog circuit. each lsb is approximately 1 db. see reading rssi on page 14 for details. 9:0 (reserved) (reserved) register 7 15:9 (reserved) (reserved) 8 tx_en initiates the transmit sequence for state machine control. note that tx_en and rx_en cannot be set to ?1? at the same time. 7 rx_en initiates the receive sequence for state machine control. note that tx_en and rx_en cannot be set to ?1? at the same time. 6:0 rf_pll_ch_no [6:0] sets tx and rx rf channel number, for example: write 0 for channel 0 (2402 mhz) write 39 for channel 39 (2441 mhz) write 78 for channel 78 (2480 mhz) register 9 15:11 (reserved) (reserved) 10:7 pa_gn[3:0] pa power level control 6:0 (reserved) (reserved) register 10 15:1 (reserved) (reserved) 0 xtal_osc_en 1: enable crystal oscillator gain block 0: disable crystal oscillator gain block 15:1 (reserved) (reserved) register 11 15 cw_mode 1: disables tx modulation; cw only. 0: normal tx mode 14:10 (reserved) (reserved) 9 rssi_dis 1: disable rssi 0: rssi operates normally. 8:0 (reserved) (reserved)
cyrf8935 document number: 001-61351 rev. *j page 22 of 40 register 23 15:3 (reserved) (reserved) 2 txrx_vco_cal_en 1: enable automat ic vco calibration with every tx/rx. 0: disable feature 1:0 (reserved) (reserved) register 27 15:11 ldo_sp_sleep sets ldo sleep current. see electrical characteristics on page 28 for register 27 settings. 10:0 (reserved) (reserved) register 29 - read only - 0x00xx 15:8 (reserved) (reserved) 7:4 rf_ver_id [3:0] this field is used to identify minor rf revisions to the design. 3 (reserved) (reserved) 2:0 digital version this field is used to identify minor digital revisions to the design. register 30 - read only - 0xf413 15:0 (reserved) (reserved) register 31 - read only 15:0 silicon id this field is used to identify silicon id. valid values are 0x1002 and 0x2002 table 10. rf register information (continued) bit no. bit name description
cyrf8935 document number: 001-61351 rev. *j page 23 of 40 table 11. framer register information bit no. bit name r/w description default register 32 15:13 preamble_len r/w 000b: 1 byte 001b: 2 bytes 010b: 3 bytes . . 111b: 8 bytes 010b 12:11 syncword_len r/w 11b: 64 bits {{reg39[15:0],reg38[1 5:0],reg37[15:0 ],reg36[15:0]} 10b: 48 bits, {reg39[15:0],reg38[15:0],reg36[15:0]} 01b: 32 bits, {reg39[15:0],reg36[15:0] 00b: 16 bits,{reg36[15:0]} 11b 10:8 trailer_len r/w 000b: 4 bits 001b: 6 bits 010b: 8 bits 011b: 10 bits . . 111b: 18 bits 000b 7:6 data_packet_type r/w 00b: non return to zero (nrz) law data 00b 5:4 fec_type r/w 00b: no fec 01b: reserved 10b: fec23 11b: reserved 00b 3:1 brclk_sel r/w selects output clock signal to brclk [7] pin: 000b: keep low 001b: crystal buffer out 010b: crystal divided by 2 011b: crystal divided by 4 100b: crystal divided by 12 101b: txclk 1 mhz 110b: apll_clk (12 mhz during tx, rx) 111b: keep low 011b 0 (reserved) w/r (reserved) 0b register 35 15 (reserved) (reserved) 14 sleep_mode w 1: enter sleep state (set cr ystal gain block to off. keep ldo regulator on (register values will be preserved). wakeup begins when spi_ss goes low. this restarts the on-chip clock oscillator to begin normal operation. 0: normal (idle) state 0b 13 (reserved) (reserved) 12 brclk_on_sleep r/w 1: crystal running at sleep mode draws more current but enables fast wakeup 0: crystal stops during sleep mode saves current but takes longer to wake up 1b note 7. brclk signal is available on bare die only, not packaged parts.
cyrf8935 document number: 001-61351 rev. *j page 24 of 40 11:8 re-transmit_times r/w max retransmit packet attempts when auto_ack= 1. 3h 7 miso_tri_opt r/w 1: miso drives low-z ev en when spi_ss = 1 (only one spi slave device on the spi) 0: miso goes tristate when spi_ss = 1 (allows multiple spi slave devices on the spi) 0b 6:0 scramble_data r/w whitening seed for data scramble. must be set the same at both ends of radio link (tx and rx). must be nonzero. 00h register 36 15:0 sync_word[15:0] r/w least significant bi ts of sync word are sent first 0000h register 37 15:0 sync_word[31:16] r/w least significant bi ts of sync word are sent first 0000h register 38 15:0 sync_word[47:32] r/w least significant bi ts of sync word are sent first 0000h register 39 15:0 sync_word[63:48] r/w least significant bi ts of sync word are sent first 0000h register 40 15:11 fifo_empty_threshold r/w during tx, this field adj usts the point at which the fifo flag signal notifies the mcu or application to indicate that the fifo register is almost empty. the best value depends on the individual application and the speed at which the mcu or application can access the fifo. 00100b 10:6 fifo_full_threshold r/w during rx, this field adjusts the point at which the fifo flag signal notifies the mcu or application to indicate that the fifo register is almost full. the best value depends on the individual application and the speed at which the mcu or application can access the fifo. 00100b 5:0 syncword_threshold r/w sets maximum number of received syncword bits that may be in error to start a packet receive. the number of bits is (syncword_threshold - 1). for example, a setting of 7 means up to 6 sync word bits can be in error 07h register 41 15 crc_on r/w 1: crc on 0: crc off 1b 14 scramble_on r/w removes long patterns of continuous 0 or 1 in transmit data. automatically restores original unscrambled data on receive. 1: scramble on 0: scramble off 0b 13 pack_length_en r/w 1: cyrf8935 regards the first byte of payload as packet length descriptor byte. 1b 12 fw_term_tx r/w 1: when fifo write point equals read point, cyrf8935 terminates tx when the fw handles packet length. 0: fw (mcu) handles length and terminates tx 1b 11 auto_ack r/w 1: after receiving data, automatically send ack to acknowledge that the packet was received correctly. 0: after receiving data, do not send ack; just go to idle. 1b table 11. framer register information (continued) bit no. bit name r/w description default
cyrf8935 document number: 001-61351 rev. *j page 25 of 40 10 pkt_fifo_polarity r/w 1: pkt flag, fifo flag active low 0: active high 0b 9:8 (reserved) r/w (reserved) 00b 7:0 crc_initial_data r/w initializati on constant for crc calculation 00h register 48 ? read only 15 crc_error r received crc error 14 fec23_error r indicate fec23 error 13:8 framer_st r framer status 7 syncword_recv r 1: syncword received. it is only available in receive status, after out receive status, always set to ?0? 6 pkt_flag r pkt flag indication 5 fifo_flag r fifo flag indication 4:0 (reserved) r (reserved) register 50 15:0 txrx_fifo_reg r/w for mcu r ead/write data between the fifo reading this register removes data from fifo; writing to this register adds data to fifo. note mcu or application access to the fifo register is byte by byte (8 bits at a time), not 16 bits as with other registers. 00h register 52 15 clr_w_ptr w 1: clear tx fifo pointer to 0 when writing this bit to ?1? it is not available in rx status. 0b 14 (reserved) w 13:8 fifo_wr_ptr r fifo write pointer 7 clr_r_ptr w 1: clear rx fifo point to 0 when writing this bit to ?1? it is not available in tx status. 0b 6 (reserved) 5:0 fifo_rd_ptr r fifo read pointer (num ber of bytes to be read by mcu) table 11. framer register information (continued) bit no. bit name r/w description default
cyrf8935 document number: 001-61351 rev. *j page 26 of 40 recommended register values the following register values are recommended for most typi cal applications. some changes may be required depending on the application. table 12. recommended register values register no. power-up reset value (hex) recommended value for applications (hex) notes silicon id 0x1002 [8] silicon id 0x2002 [8] 0 6fef 6fe1 6fe1 internal usage 1 5681 5681 5681 internal usage 2 6619 5517 5517 internal usage 4 5447 9cc9 9cd4 internal usage 5 f000 6647 651f internal usage 7 0030 0000 0000 use for setting rf frequency, and to start/stop tx/rx packets. register details in table 10 8 71af 6c90 6c90 internal usage 9 3000 1920 7920 sets tx power level. register details in table 10 10 7ffd 7ffd 7ffd crystal oscillator enabled. used for sleep patch. register details in table 10 11 4008 0008 0008 rssi enabled register details in table 10 12 0000 0000 0000 internal usage 13 4855 4880 48bf internal usage 22 c0ff 00ff 00ff internal usage 23 8005 0005 0005 register details in table 10 24 307b 0067 0067 internal usage 25 1659 1659 1659 internal usage 26 1833 19e0 1a30 internal usage 27 9100 4200 4200 8 a sleep current register details in table 10 28 1800 1800 1800 internal usage 32 1806 1000 1000 packet data type: nrz, no fec, brclk [9] = 12 divided by 4 = 3 mhz register details in table 11 33 6307 32a0 32a0 internal usage 34 030b 1000 1000 internal usage 35 1300 0f01 0f01 autoack max tx retries = 3 register details in table 11 36 0000 unique sync word unique sync word similar to a mac address register details in table 11 37 0000 unique sync word unique sync word similar to a mac address register details in table 11 38 0000 unique sync word unique sync word similar to a mac address register details in table 11 39 0000 unique sync word unique sync word similar to a mac address register details in table 11 notes 8. silicon id can be read from register 31. 9. brclk signal is available on bare die only, not packaged parts.
cyrf8935 document number: 001-61351 rev. *j page 27 of 40 40 2107 2047 2047 configure fifo flag register details in table 11 41 b800 f800 f800 crc on. scramble off first byte is packet length autoack off register details in table 11 42 fd6b fdff fdff internal usage 43 000f 000f 000f internal usage table 12. recommended register values (continued) register no. power-up reset value (hex) recommended value for applications (hex) notes silicon id 0x1002 [8] silicon id 0x2002 [8]
cyrf8935 document number: 001-61351 rev. *j page 28 of 40 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. [10, 11] storage temperature .. ............... ............... ?55 c to +125 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd ............ 0 to + 1.98 v supply voltage on v dd_io or v in relative to gnd ................. ....................... 0 to +3.63 v dc voltage applied to outputs in tristate .................................. (v ss ? 0.5) to (v dd_io + 0.5) dc input voltage ... ........... ........ (v ss ? 0.5) to (v dd_io + 0.5) current into outputs (low) ........................................ 10 ma electrostatic discharge voltage, hbm (qfn package only) rf pins (ant, antb) .......................................... >500 v analog pins xtali, xtalo .................................. >500 v all other pins ....................................................... 2000 v latch up current (jedec jesd78b, class ii) ........ 140 ma operating range range ambient temperature v in v dd_io commercial 0 c to 70 c +1.9 to 3.6 v +1.9 to 3.6 v notes 10. absolute maximum ratings indicate limits beyond which damage to the device may occur. recommended operating conditions indic ate conditions for which the device is intended to be functional, but do not guarantee specific perfo rmance limits. for guaranteed spec ifications and test conditio ns, see electrical characteristics . 11. these devices are electrostati c-sensitive. devices should be transported and stored in anti-static containers. equipment and personnel contacting the devices need to be properly grounded. cover workbenches with grounded conductive mats. 12. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v in = 3 vdc, ta = +25 c. 13. brclk signal is available on bare die only, not packaged parts. electrical characteristics for wafer and die products, rf and ac specifications are guaranteed by characterization only ? not production tested. symbol description min typ max units test condition and notes supply voltage v in dc power supply voltage range 1.9 ? 3.6 vdc input to v dd_io and v in pins current consumption i dd_tx2 current consumption ? tx ? 18.5 ? ma transmit power pa2. brclk [13] off. i dd_tx12 ? 13.7 ? ma transmit power pa12. brclk [13] off i dd_rx current consumption ? rx ? 18 ? ma brclk [13] off i dd_idle1 current consumption ? idle ? 1.1 ? ma configured for brclk [13] output off i dd_slpx current consumption ? sleep ? 1 ? a [12] temperature = +25 c. using firmware sleep patch. ( enter sleep and wakeup on page 6) register 27 = 0x1200, for v in 3.00 vdc only i dd_slpr ? 8 ? a temperature = +25 c; using firmware sleep patch ( enter sleep and wakeup on page 6) register 27 = 0x4200. i dd_slph ? 38 ? a temperature = +70 c ?c? grade part; using firmware sleep patch ( enter sleep and wakeup on page 6) register 27 = 0x4200 v ih logic input high 0.8 v ddio ? 1.2 v ddio v v il logic input low 0 ? 0.8 v i _leak_in input leakage current ? ? 10 a v oh logic output high 0.8 v dd_io ??vi oh = 100 a source v ol logic output low ? ? 0.4 v i ol = 100 a sink i _leak_out output leakage current ? ? 10 a miso in tristate t _rise_out rise/fall time (spi miso) ? 8 25 ns 7 pf cap. load
cyrf8935 document number: 001-61351 rev. *j page 29 of 40 t _rise_in rise/fall time (spi mosi) ? ? 25 ns t r_spi clk rise, fall time (spi) ? ? 25 ns req uirement for erro r-free register reading, writing. f _op operating frequency range 2400 ? 2482 mhz us age on-the-air is subject to local regulatory agency restrictions regarding operating frequency. v swr_i antenna port mismatch (z 0 = 50 ? ) ? <2:1 ? vswr receive mode. measured using lc matching circuit shown in typical application on page 12 vswr _o ? <2:1 ? vswr transmit mode. measured using lc matching circuit shown in typical application on page 12 receive section measured using lc matching circuit shown in typical application on page 12 for ber ? 0.1% rxs base receiver sensitivity (fec off) ? ?87 ? dbm room temperature only 0-ppm crystal frequency error. rxs temp ? ?84 ? dbm over temperature; 0-ppm crystal frequency error. rxs ppm ? ?84 ? dbm room temperature only 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) rxs temp+ppm ? ?80 ? dbm over temperature; 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) r xmax-sig maximum usable signal ?20 0 ? dbm room temperature only ts data (symbol) rate ? 1 ? s minimum carrier/interference ratio for ber ? 0.1%. room temperature only. ci _cochannel co-channel interference ? +9 ? db ?60-dbm desired signal ci _1 adjacent channel interference, 1-mhz offset ? +6 ? db ?60-dbm desired signal ci _2 adjacent channel interference, 2-mhz offset ? ?12 ? db ?60-dbm desired signal ci _3 adjacent channel interference, 3-mhz offset ? ?24 ? db ?67-dbm desired signal obb out-of-band blocking ? ? ?27 ? dbm 30 mhz to 12.75 ghz [14] measured with acx bf2520 ceramic filter [15] on ant. pin. ?67-dbm desired signal, ber ? 0.1%. room temperature only. electrical characteristics (continued) for wafer and die products, rf and ac specifications are guaranteed by characterization only ? not production tested. symbol description min typ max units test condition and notes notes 14. the test is run at one midband frequency, typically 2460 mhz. with blocking frequency swept in 1-mhz steps, up to 24 excepti on frequencies are allowed. of these, no more than five will persist with blocking signal reduced to ?50 dbm. for blocking frequencies below desired receive frequenc y, in-band harmonics of the out-of-band blocking signal are the most frequent cause of failure, so be sure blocking signal has adequate harmonic filtering. 15. in some applications, this filter may be incorporated into the antenna, or be approximated by the effective antenna bandwidt h.
cyrf8935 document number: 001-61351 rev. *j page 30 of 40 transmit section measured using a lc matching circuit as shown in typical application on page 12 [16] p avh rf output power ? +1 ? dbm pa0 (pa_gn = 0, reg9 = 0x1820 for silicon id [17] 0x1002 / reg9 = 0x7820 for silicon id [17] 0x2002). room temperature only. p avl ? ?11.2 ? dbm pa12 (pa_gn = 12, reg9 = 0x1e20 for silicon id [17] 0x1002 / reg9 = 0x7e20 for silicon id [17] 0x2002). room temperature only. txp fx2 second harmonic ? ?45 ? dbm measured using a lc matching circuit as shown in typical application on page 12. room temperature only. txp fx3 third and higher harmonics ? ?? ?45 ? dbm measured using a lc matching circuit as shown in typical application on page 12. room temperature only. modulation characteristics df1 avg ? 263 ? khz modulation pattern: 11110000... df2 avg ? 255 ? khz modulation pattern: 10101010... in-band spurious emission ibs_2 2-mhz offset ? ? ?20 dbm ibs_3 3-mhz offset ? ? ?30 dbm ibs_4 ? 4-mhz offset ? ?? ?30 ? dbm rf vco and pll section f step channel (step) size 1 ? mhz l 100k ssb phase noise ?75 ? dbc/hz 100-khz offset l 1m ?105 ? dbc/hz 1-mhz offset df x0 crystal oscillator frequency error ?40 ? +40 ppm relative to 12-mhz crystal reference frequency t hop rf pll settling time [18] ? 100 150 s settle to within 30 khz of final value. autocal off. t hop_ac ? 250 350 s settle to within 30 khz of final value. autocal on. ldo voltage regulator section v do dropout voltage ? 0.17 0.3 v measured during receive state electrical characteristics (continued) for wafer and die products, rf and ac specifications are guaranteed by characterization only ? not production tested. symbol description min typ max units test condition and notes notes 16. transmit power measurement is at output of matching circuit shown in typical application on page 12. 17. silicon id can be read from register 31. 18. max pll settling time is guaranteed by design (not production tested).
cyrf8935 document number: 001-61351 rev. *j page 31 of 40 spi the cyrf8935 supports a 4-wire slave spi. all of the function control is under spi command. there are four pins in the spi. spi_ss: slave selection input (active low) clk: serial clock input mosi: master out slave in miso: master in slave out spi transaction formats and timing spi read and write data is always in multiple s of bytes. the first byte (msb) consists of the r/w direction bit, followed by a 7-bit register address. following this byte, there are one or more data bytes. when using the spi to access the internal registers, note that some registers are accessed differently than others. table 13 shows the three types of registers: figure 17. single-byte data format figure 18. two-byte data format figure 19. multi-byte data format [19] table 13. spi access methods for various registers group no. register number(s) description access method group 1 0 to 31 rf/analog registers wri te an even number of data bytes read out any number of data bytes; register high byte is read out first group 2 32 to 42, 52 state and framer configur ation registers read/writeable any data bytes group 3 50 fifo read/write always byte by byte spi_ss clk mosi w/r a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 miso s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 t sss t ssh t1 t ss_hd spi_ss clk mosi w/r a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 miso s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 t1 t1 t sss t ssh t ss_hd spi_ss clk mosi w/r a6 a5 a4 a3 a2 a1 a0 d7 d6 d7 d7 d7 d0 miso s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d7 d7 d7 d7 d0 d7 d0 d0 d0 d0 d0 d0 d0 d0 address address + n address + 1 t1 t1 t1 t sss t ssh t ss_hd note 19. for all registers except register 50, the internal register address auto-increments by one when reading or writing more than two bytes of data in a single spi transaction. this is an optional, built-in feature designed to save time wh en reading or writing multiple registers in ascending sequence.
cyrf8935 document number: 001-61351 rev. *j page 32 of 40 specifications w/r bit: ? 0: write spi ? 1: read spi dx: data bits from spi master. when reading, these bits are ignored. dx: data bits from spi slave. when writing, dx is the same as sx. sx: data from reg48[15:8], msb first (status byte). figure 20. spi timing diagram spi_ss clk mosi miso t sckh t sckl t sss t ssh t ssu t shd t sdo t sdo1 t sdo2 t sck t ss_su table 14. spi timing requirements timing parameter min max unit notes t sss 20 ? ns setup time from assertion of spi_ss to clk edge t ssh 200 ? ns hold time required deassertion of spi_ss t sckh 40 ? ns clk minimum high time t sckl 40 ? ns clk minimum low time t sck 83 ? ns maximum clk clock is 12 mhz t ssu 30 ? ns mosi setup time t shd 10 ? ns mosi hold time t ss_su 10 ? ns before spi_ss enable, clk hold low time requirement t ss_hd 200 ? ns minimum spi inactive time t sdo ? 35 ns miso setup time, ready to read t sdo1 ? 5 ns if miso is configured as tristate, miso assertion time t sdo2 ? 250 ns if miso is configured as tristate, miso deassertion time t1 min_r50 350 ? ns when reading register 50 (fifo) t1 min 83 ? ns when writing register 50 (fifo), or r eading/writing any registers other than register 50.
cyrf8935 document number: 001-61351 rev. *j page 33 of 40 electrical operati ng characteristics figure 21. typical transmit evm, evm spectrum, tx eye figure 22. evm equip. setup
cyrf8935 document number: 001-61351 rev. *j page 34 of 40 state diagram off idle vco_wait sleep wake up vco_sel rx packet tx packet tx ack rx ack v c o _ c a l tx_en rx_en s l e e p w a k e u p ack received n a c k n o a u t o _ a c k n o a u t o _ a c k no crc error p a c k et e r r o r a u t o _ a ck a uto_ a c k
cyrf8935 document number: 001-61351 rev. *j page 35 of 40 ordering information ordering code definitions ordering code [20] package temperature range cyrf8935a-24lqxc 24 pin (4 4 0.55 mm) sawn qfn commercial cyrf8935a-4x14c die (14-mil) in waffle pack commercial cyrf8935a-4xw14c die (14-mil) in wafer form commercial thermal rating c = commercial, i = industrial, e = extended cy rf part number 8935 ( 24 lqx (c , i , e) a internal revision code marketing code / xxx ) company id : cy = cypress radio frequency : rf = wireless ( ) product family kgd level /package type/ die thickness 24 - pin sawn qfn package x = pb- free note 20. for die and wafer sales, consult your cypress sales representative.
cyrf8935 document number: 001-61351 rev. *j page 36 of 40 package diagram figure 23. 24-pin qfn (4 4 0.55 mm) lq24a 2. 65 2.65 e-pad (sawn) package outline, 001-13937 001-13937 *e
cyrf8935 document number: 001-61351 rev. *j page 37 of 40 acronyms document conventions units of measure table 15. acronyms used in this document acronym description ack acknowledge (packet received, no errors) ber bit error rate bom bill of materials cmos complementary metal oxide semiconductor cob chip on board crc cyclic redundancy check dut device under test emc electromagnetic compatibility evm error vector magnitude fec forward error correction fer frame error rate gfsk gaussian frequency-shift keying hbm human body model ism industrial, scientific, and medical irq interrupt request mac media access control mcu microcontroller unit nrz non return to zero ota over-the-air pll phase locked loop pn pseudo-noise qfn quad flat no-leads rssi received signal strength indication rf radio frequency rx receive tx transmit vco voltage controlled oscillator wep wired equivalent privacy table 16. units of measure symbol unit of measure c degree celsius db decibels dbc decibel relative to carrier dbm decibel-milliwatt hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? s microsecond ? v microvolts ? vrms microvolts root-mean-square ? w microwatts ma milliampere ms millisecond mv millivolts na nanoampere ns nanosecond nv nanovolts ? ohm pp peak-to-peak ppm parts per million ps picosecond sps samples per second v volts vdc volts direct current
cyrf8935 document number: 001-61351 rev. *j page 38 of 40 document history page document title: cyrf8935, wirele ssusb?-nl 2.4 ghz low power radio document number: 001-61351 rev. ecn no. orig. of change submission date description of change ** 2963911 hemp 06/28/2010 new data sheet. *a 3039285 hemp 09/27/2010 updated block diagram updated init, xtal osc, rxsens measurement. revised state diagram and package diagram. updated functional description. payload format nrz only. revised power control table; showed absolute, not relative power. deleted reference to nak. added rssi curve. corrected reg. 7, 32, 41 definition. updated recommended register values table. updated absolute maximum voltages and temperature range. updated rx i typical value. used paxx to show power level settings. updated third harmonics and v do values. added die information to ordering code. *b 3112690 hemp 12/16/2010 no technical updates; integrated with eros. *c 3296429 hemp / kkcn 06/29/2011 removed preliminary status from datasheet. modified product description. changed gnd1...gnd5 to gnd in the logic block diagram. added note about brclk?s availability only on bare die. replaced 32-pin with 24-pin and package details. updated ?enter sleep and wakeup? functional description. updated figures 7 and 8. updated typical application diagram. adding ?setting the radi o frequency? section. modified ?crystal oscillator? section deleted brclk pin, ckpha signal, and fec13 mode. updated ?reading rssi? section. updated register definitions updated various electrical specs. updated ordering information. *d 3363798 hemp 09/07/2011 added information on die and wafer parts in features , ordering information , and ordering code definitions . *e 3440958 hemp 11/17/2011 updated power-on and register initialization sequence section. updated initialization timing requirements table. updated initialization flowchart . updated typical application and reset pull-up circuit diagram. added reset pull-up section. added register 27 in rf register information table. added footnote for rf pll settling time. updated t sdo max value. *f 3794924 selv 12/10/2012 updated logic diagram. added notes 1 , 3 , 4 , 5 , 7 , 9 , and 13 . updated values of t sckh , t sckl , t ssu parameters in ta b l e 1 4 . updated package diagram as per spec 001-13937 *e.
cyrf8935 document number: 001-61351 rev. *j page 39 of 40 *g 3841304 selv 01/10/2013 updated typical application : updated ta b l e 6 under transmit power control to include values of register 9 for each silicon id. added note 6 and referred the same note in both silicon id columns. updated register definitions : updated details of ?register 31 - read only? in table 10 . updated table 12 under recommended register values to include recommended value for applications for each silicon id. added note 8 and referred the same note for silicon id columns. updated electrical characteristics : updated test condition and notes of p avh and p avl parameters to include values of register 9 for each silicon id. added note 17 and referred the same no te for silicon ids in p avh and p avl parameters. *h 3928385 selv 03/11/2013 updated enter sleep and wakeup , receive timing , and reset pull-up sections. *i 3980337 selv 04/24/2013 updated register definitions : updated table 12 under recommended register values with new values in columns ?silicon id 0x1002? and ?silicon id 0x2002? for registers 7, 23, 32, 33, 34, 35, and 41. *j 4036152 selv 06/21/2013 updated register definitions : updated table 12 under recommended register values with new value in column ?silicon id 0x2002? for register 26. completing sunset review. document history page (continued) document title: cyrf8935, wirele ssusb?-nl 2.4 ghz low power radio document number: 001-61351 rev. ecn no. orig. of change submission date description of change
document number: 001-61351 rev. *j revised june 21, 2013 page 40 of 40 wirelessusb and encore are trademarks of cypress semiconductor corporation. all products and company names mentioned in this do cument may be the trademarks of their respective holders. cyrf8935 ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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